{"type":"rich","version":1.0,"title":"Fully containerized FPGA generation from Chisel sources using FuseSoc","width":2305,"html":"<a href=\"https://asciinema.org/a/405850\" target=\"_blank\"><img src=\"https://asciinema.org/a/405850.png\" alt=\"Fully containerized FPGA generation from Chisel sources using FuseSoc\" width=\"2305\"></a>","height":1784,"author_name":"carlosedp","author_url":"https://asciinema.org/~carlosedp","provider_name":"asciinema","provider_url":"https://asciinema.org/","thumbnail_height":1784,"thumbnail_url":"https://asciinema.org/a/405850.png","thumbnail_width":2305}