{"type":"rich","version":1.0,"title":"Building a tiny RISC-V core for Xilinx FPGA with complete  FOSS toolchain","width":2132,"html":"<a href=\"https://asciinema.org/a/314183\" target=\"_blank\"><img src=\"https://asciinema.org/a/314183.png\" alt=\"Building a tiny RISC-V core for Xilinx FPGA with complete  FOSS toolchain\" width=\"2132\"></a>","height":1112,"author_name":"ruinland","author_url":"https://asciinema.org/~ruinland","provider_name":"asciinema","provider_url":"https://asciinema.org/","thumbnail_height":1112,"thumbnail_url":"https://asciinema.org/a/314183.png","thumbnail_width":2132}