In this cast I use WAL to determine the number of cycles the SERV and VexRiscv cores need to execute one instruction on average.
To compute this value I analyze the number if instructions that where executed by each core and divided it by the number of clock cycles of the complete waveform.
In the SERV core whenever the execution of a new instruction starts the signal wb_ibus_ack on the instruction bus is set to high. Similarily, in the VexRiscv core we know an instruction was executed when the isFiring signal of the last pipeline stage is set to high.
;; SERV
(load "serv-addi.vcd" serv)
; create some conveniant aliases
(alias clk TOP.servant_sim.dut.cpu.clk)
(alias start TOP.servant_sim.dut.wb_ibus_ack)
; this function returns the number of clock cycles in the waveform
; which is the number of indices / 2
(defun ticks () (/ MAX-INDEX 2))
; calculate avg. number of cycles between instructions
; and store it in the serv variable
(set [serv (/ (ticks) (length (find (&& clk start))))])
; unload waveform and remove aliases
(unload serv)
(unalias clk start)
;; VexRiscV
(load "vex-addi.vcd" vex)
(alias clk TOP.VexRiscv.clk)
(alias start TOP.VexRiscv.writeBack_arbitration_isFiring)
(set [vex (/ (ticks) (length (find (&& clk start))))])
(printf "SERV: %d\n" serv)
(printf "VEX : %d\n" vex)
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