Fully containerized FPGA generation from Chisel sources using FuseSoc

Link

Append ?t=30 to start the playback at 30s, ?t=3:20 to start the playback at 3m 20s.

Embed image link

Use snippets below to display a screenshot linking to this recording.
Useful in places where scripts are not allowed (e.g. in a project's README file).

HTML:

Markdown:

Embed the player

If you're embedding on your own page or on a site which permits script tags, you can use the full player widget:

Paste the above script tag where you want the player to be displayed on your page.

See embedding docs for additional options.

You can download this recording in asciicast v2 format, as a .cast file.

Download

Replay in terminal

You can replay the downloaded recording in your terminal using the asciinema play command:

asciinema play 405850.cast

If you don't have asciinema CLI installed then see installation instructions.

Use with stand-alone player on your website

Download asciinema player from the releases page (you only need .js and .css file), then use it like this:

<!DOCTYPE html>
<html>
<head>
  <link rel="stylesheet" type="text/css" href="asciinema-player.css" />
</head>
<body>
  <div id="player"></div>
  <script src="asciinema-player.min.js"></script>
  <script>
    AsciinemaPlayer.create(
      '/assets/405850.cast',
      document.getElementById('player'),
      { cols: 158, rows: 55 }
    );
  </script>
</body>
</html>

See asciinema player quick-start guide for full usage instructions.

While this site doesn't offer GIF conversion at the moment, you can still do it yourself with the help of asciinema GIF generator utility - agg.

Once you have it installed run the following command to create GIF file:

agg https://asciinema.org/a/405850 405850.gif

Or, if you already downloaded the recording file:

agg 405850.cast 405850.gif

Check agg --help for all available options. You can change font family and size, select color theme, adjust speed and more.

See agg manual for full usage instructions.

Fully containerized FPGA generation from Chisel sources using FuseSoc

More by carlosedp

ChiselV simulation on Verilator with UART 00:43

FuseSoc chiselblinky project generation 02:35

Scala mill build tool completion script for Zsh 00:26

FPGA Bitstream for Xilinx Artix7 running on FuseSoc containers with open source toolchain 04:38